The present invention relates to a method and apparatus for controlling the rise time and fall time of a differential output digital signal. More specifically, the present invention provides for a method and apparatus to reshape a data input based upon a clock signal, provide n parallel connected output drivers, provide n sets of control signals to control the edge-rate of the n output drivers, and the output drivers provide minimum over-shoot, low jitter, low signal skew, and a well controlled rise and fall time over varied common mode voltages.
Low Voltage Differential Signaling (hereinafter referred to as LVDS) is a technology used in data transmission systems. A low voltage differential signal produced by a line driver typically has peak-to-peak amplitudes in the range from 250 mV to 450 mV. The low voltage swing minimizes power dissipation, while maintaining high transmission speeds. Typical transmission speeds are over 100 Mbps (Mega-bits per second).
In some applications it is necessary for a line driver to produce a differential output that has a rise and fall time within specified limits. Very fast rise and fall times tend to cause a power supply line bounce condition, where the sudden increase in current driven into the power supply line causes a glitch to appear on the power supply line. Also, very fast rise and fall times may result in a glitch in the differential output signal. Glitches that appear in the power supply lines and the differential output signals can be limited by increasing the rise and fall times accordingly.
One technique used to increase the transition time (rise and fall) for a differential line driver was to increase its gate input transition time, which resulted in reducing the driver""s effective data rate and increasing noise jitter due to the slower transition time. Also, the output waveforms tend to distort when the common mode voltage increases (i.e. the common mode voltage is increased from 0.8V to 2.5V) due to the non-linearity of the small-signal trans-conductance from the gate to the channel (gm) of the output transistors of the differential line driver. Additionally, over the common mode voltage range, the output signal of the differential line driver can have undesirable over-shoot and under-shoot causing distortion in the output signal (common mode induced jitter).
In accordance with the invention, the above and other problems are solved by an apparatus and method for generating a differential output signal. Briefly stated, the present invention relates to differential output driver circuits that produce a differential output signal in response to an input data signal. The differential output driver circuit provides for a controlled edge rate in the differential output signal when the input data signal changes logic states. Control signals are generated using an adjustable delay circuit, each subsequent control signal being delayed in time from the preceding control signal by a unit delay time. The control signals control N output drivers, each of the N output drivers having an output signal coupled to the differential output signal. Each of the N output drivers contributes a portion of the differential output signal. When the input data signal changes from one logic state to another, the differential output signal will have a defined edge rate determined by the unit delay time, N, and the contributing portion from each of the N output drivers. In one example, the unit delay time is determined by a delay time through a buffer that has a controlled current limit. The controlled current limit is provided by a current source that is compensated for semiconductor processing variations and temperature variations. Variations in semiconductor processing are corrected by producing a current that is inversely proportional to the trans-conductance of a MOS transistor reference device. Since the current limit in the buffer is raised for slower transistors (lower trans-conductance), the unit delay time is maintained within tolerable limits when the process parameters vary. The differential output driver circuit is compensated to provide minimum over-shoot, low jitter, low distortion, low signal skew, and a controlled rise and fall times over varied common mode voltages.
In accordance with an aspect of the invention, a differential output signal is produced in response to an input data signal. A control logic circuit produces control signals corresponding to the input data, and a driver circuit produces the differential output signal in response to the control signals. The driver circuit has N driver cells, each of the N driver cells generating a respective output signal in response to a respective control signal. The respective output signals of the N driver cells are arranged such that each of the N driver cells provides a portion of the differential output signal.
In accordance with a further aspect of the invention, a change in the input data signal results in a change in the control signals for one of the N driver cells at a time different from the other of the N driver cells such that the rise time of the differential output signal is proportional to the time difference.
In accordance with yet a further aspect of the invention, a change in the input data signal results in a change in the control signals for one of the N driver cells at a time different from the other of the N driver cells such that the fall time of the differential output signal is proportional to the time difference.
In accordance with another feature of the invention, a control logic circuit has N delay circuits, each of the N delay circuits including: a delay cell having an input and output, the delay cell is current limited by a current limit amount, a delay time corresponds to the delay between an input change and an output change, and the delay time is proportional to the current limit amount.
In accordance with yet another feature of the invention, the control logic circuit includes a delay circuit with an input and output, a delay time from the input to the output is controlled by a current reference, and the current reference is compensated to reduce variations in the delay time. In one embodiment of the invention, the current reference includes a MOS transistor that has a trans-conductance parameter, the MOS transistor is arranged to conduct a current that is proportional to the trans-conductance parameter, a difference circuit provides another current that corresponds to a difference between a temperature compensated current and the current, and a reference MOS transistor is arranged to conduct a bias current that corresponds to a sum of the another temperature compensated current and the another current such that the bias current is inversely proportional to the trans-conductance and variations in the delay time due to changes in trans-conductance are reduced. In another embodiment of the invention, the current reference includes a resistor having a resistor value and a temperature coefficient, a temperature compensated current is coupled to the resistor to produce a gate voltage that is independent of temperature, a MOS transistor is arranged to conduct a current that is proportional to the gate voltage, a difference circuit provides another current that corresponds to a difference between another temperature compensated current and the current, and a reference MOS transistor is arranged to conduct a bias current that corresponds to a sum of the another temperature compensated current and the another current, such that the bias current is independent of temperature and variations in the delay time due to changes in temperature are reduced.
According to a feature of the invention, a differential output signal is produced in response to an input data signal. The driver circuit has N driver cells, each of the N driver cells generating a respective output signal in response to a respective control signal. A current source provides a controlled current. The controlled current is coupled to the driver circuit such that each respective outputs signal corresponds to a portion of the controlled current. The sum of the portions from each respective output signal corresponds to the controlled current. In one embodiment of the invention, a current source provides power to the driver cells, the driver cells consume current when enabled; and the driver cells do not consume current when disabled. A standby circuit loads the current source when active, and does not load the current source when inactive. The standby circuit is activated prior to enabling the driver cells that are disabled, and is deactivated after the driver cells are enabled. The standby circuit provides a load to the current source that is comparable to the load on the current source when the driver cells are enabled, such that enabling the driver cells does not cause a glitch in the differential output signal.
According to another feature of the invention, a driver cell is provided for that includes: a first, second, third and fourth switching element, each switching element conducts when activated by a respective control signal. The first and second switching elements are coupled to a first power connection. The third and fourth switching elements are coupled to a second power connection. The second and third switching elements are arranged such that when activated the differential output signal is a polarity. The first and fourth switching elements are arranged such that when activated the differential output signal is another polarity.
According to yet another feature of the invention, a driver cell is provided for where each driver cell further includes an anti-glitch circuit. Each anti-glitch circuit minimizes glitches from appearing in the differential output signal. Each anti-glitch circuit may include a first, second, third and fourth capacitor coupled to each respective switching element.
According to another aspect of the invention, an apparatus generates a differential output signal from an input data signal. The apparatus includes a control logic circuit and a driver circuit. The control logic circuit produces control signals related to the input data signal. The driver circuit produces the differential output signal in response to the control signals. The driver circuit includes a plurality of driver cells, each generating an output signal in response to associated control signals, the driver output signals being arranged so that each of the plurality of driver cells provides a portion of the differential output signal. In one embodiment, a group of the plurality of driver cells are commonly controlled by control signals. In another embodiment, control signals are associated with a separate group of the plurality of driver cells, wherein the control signals commonly control the associated separate group of the plurality of driver cells such that the portion of the differential output signal provided by the separate group of the plurality of driver cells is different from the portion provided by another of the plurality of driver cells. Alternatively, the portion of the differential output signal provided by one of the plurality of driver cells may be different from the portion of the differential output signal provided by another of the plurality of driver cells. Thus, each output driver cell may provide a different level of output signal.
According to an aspect of the invention, an apparatus for generating a differential output signal from an input data signal includes means for producing a time delay, means for producing a differential output signal corresponding to the input data signal, and means for controlling an edge rate of the differential output signal such that an edge rate in the differential output signal is proportional to the time delay.
According to a further aspect of the invention, the means for controlling the edge rate includes means for producing a first control signal from the input data signal, and means for producing a second control signal. The second control signal is the same as the first control signal skewed in time by the time delay. A means for producing the differential output signal in response to the first and second control signals such that the time delay corresponds to an edge rate in the differential output signal. Also, the means for producing a time delay may include means for generating a current level, the current level being inversely proportional to the time delay.
According to yet a further feature of the invention, the means for generating a differential output signal includes means for generating N equal outputs staggered over equal time intervals. Each of the N outputs corresponding to an equal portion of the differential output signal. The resulting differential output signal has an edge rate that corresponds to the N equal time intervals. Also, a means for maintaining a constant edge rate is provided such that the differential output signal has a constant edge rate for varying output common mode voltages.
According to an aspect of the invention, a method of generating a differential output signal from an input data signal provide for generating a control signal in response to a change in the input data at an initial time, generating another control signal in response a change in the control signal at a subsequent time, producing an output signal in response to the control signal, producing another output signal in response to the another control signal, and summing together the output signal and the another output signal to produce the differential output signal, the edge rate in the differential output corresponding to the difference between the initial time and the subsequent time. Also, a time delay is generated based upon at least one semiconductor processing parameter, the difference between the initial time and the subsequent time is proportional to the time delay.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detail description of presently preferred embodiments of the invention, and to the appended claims.